The present invention relates generally to the fields of semiconductors and integrated circuits and, more particularly, to structures, techniques, and processes for providing interconnects and for interconnecting devices in integrated circuits.
Of the numerous requirements for advanced very large scale integrated (VLSI) silicon microelectronics, power dissipation per unit area, speed, packing density and radiation hardness are especially important. Power dissipation and speed have forced an evolutionary path from PMOS to NMOS to NMOS E/D and to the currently used CMOS. As evidenced by the large number of publications, CMOS on insulating substrates is receiving increased attention due to its potential as the next generation in MOS evolution.
Silicon on insulators (SOI) is a technology which is receiving increasing attention for next generation integrated circuits requiring significantly reduced power dissipation and gate delay along with increased packing density and isolation. Furthermore, as lateral scaling continues, vertical dimensions of integrated circuits must be reduced: n.sup.+ and p.sup.+ source and drain regions 100 nanometers (nm) deep or less will facilitate the design and fabrication of sub-500 nm gate length MOSFETs with long channel behavior.
Silicon on sapphire (SOS) is the most mature SOI candidate with the following advantageous characteristics: large area single crystal film, full dielectric isolation with virtually zero substrate capacitance, a track record for application to VLSI and commercial availability of well characterized material (up to 5 inch wafers).
Lau, et al (S. Lau, S. Matteson, J. Mayer, P. Revesz, J. Gyulai, J. Roth, T. Sigmon and T. Cass, Applied Physics Letters, 34, 76 (1979)) originally demonstrated that the crystalline quality of SOS films could be improved by utilizing a silicon implant to create a buried amorphous layer followed by a thermal anneal which causes regrowth of an improved film from the surface downward, a process known as Solid Phase Epitaxy (SPE). Inoue and Yoshii applied the SPE technique to thin (185 nm) films (T. Inoue, T. Yoshii, Applied Physics Letters 36 (1), 64 (1980)) and reported significantly improved device performance in a double SPE (DSPE) process (T. Yoshii, S. Taguchi, T. Inoue and H. Tango, Japan Journal of Applied Physics, 21 (supl. 21-1), 175 (1982)).
Another DSPE process is described by R. Reedy, T. Sigmon and L. Christel in Applied Physics Letters, 42, 707 (1983) hereby incorporated by reference in its entirety. That described DSPE process uses a first 1.times.10.sup.15 cm.sup.-2 28 Si implant at 170 keD, followed by a double anneal: 550.degree. C./2 hours 1050.degree. C./1 hour in nitrogen. The sequence is then repeated but with a 100 keV, 2.times.10.sup.15 cm.sup.-2 implant. Adequate thermal contact must be provided during implant to prevent self annealing. Further details of this DSPE process are also described in "THIN (100 nm) SOS FOR APPLICATION TO BEYOND VLSI MICROELECTRONICS", Ronald E. Reedy and Graham A. Garcia, Materials Research Society Symposium Proceedings, volume 107, p. 365-376, hereby incorporated by reference in its entirety.
Conventional CMOS devices are fabricated by defining the gate (G), source (S), and drain (D) regions in either bulk silicon or 500 nm thick SOS. For conventional SOS, 500 nm thickness is required to insure high device performance. Generally, the entire structure is then coated with an insulating layer and contact holes are opened to interconnect devices in the integrated circuit via a metallization layer which is applied over the insulating layer and into the contact holes to contact the devices. The area requirement of the contact window is up to 50% of the transistor area. For short (submicron)/gate lengths the S and D junctions must be 150 nm deep or less. Utilizing current techniques, considerable difficulty is encountered in forming these junctions and greater difficulty is encountered in making contact to them. As device dimensions approach 150 nm, it is envisioned that junction depths of 50 nm or less will be required. It is expected that forming and contacting such junctions by conventional, known techniques will be an extremely low yield process. Further, the step height for contact formation is determined by the oxide thickness necessary to ensure isolation as well as to reduce metal to substrate capacitance. The metallization layer must be thick enough to cover this step height. Etching thick metal lines is difficult especially where the metal becomes thinner at steps, leading to electro-migration failure.